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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-18 15:48:35 -0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-21 21:51:27 +0200
commit460d0d444822e9032a2573fc051b45c68b89a97a (patch)
tree1428651bfc2aec68811555d9155b0aa16eb66c2a /drivers/clk/sunxi/Makefile
parentf2e0a53271a439a2ab142645867f0cde45b2b3cd (diff)
clk: sunxi: Add a driver for the PLL2
The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk/sunxi/Makefile')
-rw-r--r--drivers/clk/sunxi/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index f5a35b82cc1a..c658a18ba7cb 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -4,6 +4,7 @@
obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
obj-y += clk-simple-gates.o