msm: Rename msmfalcon/apqfalcon to sdm660/sda660

Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".

Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>

26 files changed, 344 insertions, 344 deletions

diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
index bfb697347ec5..3829f6aec124 100644
--- a/drivers/clk/msm/Kconfig
+++ b/drivers/clk/msm/Kconfig
@@ -7,7 +7,7 @@ config COMMON_CLK_MSM
 	  This support clock controller used by MSM devices which support
 	  global, mmss and gpu clock controller.
 	  Say Y if you want to support the clocks exposed by the MSM on
-	  platforms such as msm8996, msm8998, msmfalcon etc.
+	  platforms such as msm8996, msm8998 etc.
 
 config MSM_CLK_CONTROLLER_V2
 	bool "QTI clock driver"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b5dd556b3f96..5a6b62892328 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -153,33 +153,33 @@ config MSM_MMCC_8996
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
 
-config MSM_GCC_FALCON
-	tristate "MSMFALCON Global Clock Controller"
+config MSM_GCC_660
+	tristate "SDM660 Global Clock Controller"
 	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	---help---
 	  Support for the global clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to use peripheral devices such as UART, SPI, I2C,
 	  USB, UFS, SD/eMMC, PCIe, etc.
 
-config MSM_GPUCC_FALCON
-	tristate "MSMFALCON Graphics Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_GPUCC_660
+	tristate "SDM660 Graphics Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the graphics clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support graphics controller devices which will
 	  be required to enable those device.
 
-config MSM_MMCC_FALCON
-	tristate "MSMFALCON Multimedia Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_MMCC_660
+	tristate "SDM660 Multimedia Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support multimedia devices such as display,
 	  video encode/decode, camera, etc.
 
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index a63065c97319..481cda67974b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
-obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o
+obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
-obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o
-obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o
+obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o
+obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
 obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index d14c32bffe14..9332e99e642b 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -656,75 +656,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 	.num_clks = ARRAY_SIZE(msm8996_clks),
 };
 
-/* msmfalcon */
-DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
+/* sdm660 */
+DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
 								19200000);
-DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
 						QCOM_SMD_RPM_BUS_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
 						   QCOM_SMD_RPM_MMAXI_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
 						QCOM_SMD_RPM_AGGR_CLK, 2);
-DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk,
+DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
 						QCOM_SMD_RPM_MISC_CLK, 1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
-
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
+
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
 							ln_bb_clk1_pin_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
 							ln_bb_clk2_pin_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
 							ln_bb_clk3_pin_ao, 0x3);
 
-static struct clk_hw *msmfalcon_clks[] = {
-	[RPM_XO_CLK_SRC]	= &msmfalcon_cxo.hw,
-	[RPM_XO_A_CLK_SRC]	= &msmfalcon_cxo_a.hw,
-	[RPM_SNOC_CLK]		= &msmfalcon_snoc_clk.hw,
-	[RPM_SNOC_A_CLK]	= &msmfalcon_snoc_a_clk.hw,
-	[RPM_BIMC_CLK]		= &msmfalcon_bimc_clk.hw,
-	[RPM_BIMC_A_CLK]	= &msmfalcon_bimc_a_clk.hw,
-	[RPM_QDSS_CLK]		= &msmfalcon_qdss_clk.hw,
-	[RPM_QDSS_A_CLK]	= &msmfalcon_qdss_a_clk.hw,
-	[RPM_RF_CLK1]		= &msmfalcon_rf_clk1.hw,
-	[RPM_RF_CLK1_A]		= &msmfalcon_rf_clk1_ao.hw,
-	[RPM_RF_CLK1_PIN]	= &msmfalcon_rf_clk1_pin.hw,
-	[RPM_RF_CLK1_A_PIN]	= &msmfalcon_rf_clk1_ao_pin.hw,
-	[RPM_AGGR2_NOC_CLK]	= &msmfalcon_aggre2_noc_clk.hw,
-	[RPM_AGGR2_NOC_A_CLK]	= &msmfalcon_aggre2_noc_a_clk.hw,
-	[RPM_CNOC_CLK]		= &msmfalcon_cnoc_clk.hw,
-	[RPM_CNOC_A_CLK]	= &msmfalcon_cnoc_a_clk.hw,
-	[RPM_IPA_CLK]		= &msmfalcon_ipa_clk.hw,
-	[RPM_IPA_A_CLK]		= &msmfalcon_ipa_a_clk.hw,
-	[RPM_CE1_CLK]		= &msmfalcon_ce1_clk.hw,
-	[RPM_CE1_A_CLK]		= &msmfalcon_ce1_a_clk.hw,
-	[RPM_DIV_CLK1]		= &msmfalcon_div_clk1.hw,
-	[RPM_DIV_CLK1_AO]	= &msmfalcon_div_clk1_ao.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1_ao.hw,
-	[RPM_LN_BB_CLK1_PIN]	= &msmfalcon_ln_bb_clk1_pin.hw,
-	[RPM_LN_BB_CLK1_PIN_AO]	= &msmfalcon_ln_bb_clk1_pin_ao.hw,
-	[RPM_LN_BB_CLK2]	= &msmfalcon_ln_bb_clk2.hw,
-	[RPM_LN_BB_CLK2_AO]	= &msmfalcon_ln_bb_clk2_ao.hw,
-	[RPM_LN_BB_CLK2_PIN]	= &msmfalcon_ln_bb_clk2_pin.hw,
-	[RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw,
-	[RPM_LN_BB_CLK3]	= &msmfalcon_ln_bb_clk3.hw,
-	[RPM_LN_BB_CLK3_AO]	= &msmfalcon_ln_bb_clk3_ao.hw,
-	[RPM_LN_BB_CLK3_PIN]	= &msmfalcon_ln_bb_clk3_pin.hw,
-	[RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw,
-	[RPM_CNOC_PERIPH_CLK]	= &msmfalcon_cnoc_periph_clk.hw,
-	[RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw,
-	[MMSSNOC_AXI_CLK]	= &msmfalcon_mmssnoc_axi_clk.hw,
-	[MMSSNOC_AXI_A_CLK]	= &msmfalcon_mmssnoc_axi_a_clk.hw,
+static struct clk_hw *sdm660_clks[] = {
+	[RPM_XO_CLK_SRC]	= &sdm660_cxo.hw,
+	[RPM_XO_A_CLK_SRC]	= &sdm660_cxo_a.hw,
+	[RPM_SNOC_CLK]		= &sdm660_snoc_clk.hw,
+	[RPM_SNOC_A_CLK]	= &sdm660_snoc_a_clk.hw,
+	[RPM_BIMC_CLK]		= &sdm660_bimc_clk.hw,
+	[RPM_BIMC_A_CLK]	= &sdm660_bimc_a_clk.hw,
+	[RPM_QDSS_CLK]		= &sdm660_qdss_clk.hw,
+	[RPM_QDSS_A_CLK]	= &sdm660_qdss_a_clk.hw,
+	[RPM_RF_CLK1]		= &sdm660_rf_clk1.hw,
+	[RPM_RF_CLK1_A]		= &sdm660_rf_clk1_ao.hw,
+	[RPM_RF_CLK1_PIN]	= &sdm660_rf_clk1_pin.hw,
+	[RPM_RF_CLK1_A_PIN]	= &sdm660_rf_clk1_ao_pin.hw,
+	[RPM_AGGR2_NOC_CLK]	= &sdm660_aggre2_noc_clk.hw,
+	[RPM_AGGR2_NOC_A_CLK]	= &sdm660_aggre2_noc_a_clk.hw,
+	[RPM_CNOC_CLK]		= &sdm660_cnoc_clk.hw,
+	[RPM_CNOC_A_CLK]	= &sdm660_cnoc_a_clk.hw,
+	[RPM_IPA_CLK]		= &sdm660_ipa_clk.hw,
+	[RPM_IPA_A_CLK]		= &sdm660_ipa_a_clk.hw,
+	[RPM_CE1_CLK]		= &sdm660_ce1_clk.hw,
+	[RPM_CE1_A_CLK]		= &sdm660_ce1_a_clk.hw,
+	[RPM_DIV_CLK1]		= &sdm660_div_clk1.hw,
+	[RPM_DIV_CLK1_AO]	= &sdm660_div_clk1_ao.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1_ao.hw,
+	[RPM_LN_BB_CLK1_PIN]	= &sdm660_ln_bb_clk1_pin.hw,
+	[RPM_LN_BB_CLK1_PIN_AO]	= &sdm660_ln_bb_clk1_pin_ao.hw,
+	[RPM_LN_BB_CLK2]	= &sdm660_ln_bb_clk2.hw,
+	[RPM_LN_BB_CLK2_AO]	= &sdm660_ln_bb_clk2_ao.hw,
+	[RPM_LN_BB_CLK2_PIN]	= &sdm660_ln_bb_clk2_pin.hw,
+	[RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw,
+	[RPM_LN_BB_CLK3]	= &sdm660_ln_bb_clk3.hw,
+	[RPM_LN_BB_CLK3_AO]	= &sdm660_ln_bb_clk3_ao.hw,
+	[RPM_LN_BB_CLK3_PIN]	= &sdm660_ln_bb_clk3_pin.hw,
+	[RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw,
+	[RPM_CNOC_PERIPH_CLK]	= &sdm660_cnoc_periph_clk.hw,
+	[RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw,
+	[MMSSNOC_AXI_CLK]	= &sdm660_mmssnoc_axi_clk.hw,
+	[MMSSNOC_AXI_A_CLK]	= &sdm660_mmssnoc_axi_a_clk.hw,
 
 	/* Voter Clocks */
 	[BIMC_MSMBUS_CLK]	= &bimc_msmbus_clk.hw,
@@ -746,16 +746,16 @@ static struct clk_hw *msmfalcon_clks[] = {
 	[CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw,
 };
 
-static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = {
-	.clks = msmfalcon_clks,
+static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
+	.clks = sdm660_clks,
 	.num_rpm_clks = RPM_CNOC_PERIPH_A_CLK,
-	.num_clks = ARRAY_SIZE(msmfalcon_clks),
+	.num_clks = ARRAY_SIZE(sdm660_clks),
 };
 
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
 	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996},
-	{ .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon},
+	{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -766,21 +766,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct rpm_cc *rcc;
 	struct clk_onecell_data *data;
-	int ret, is_8996 = 0, is_falcon = 0;
+	int ret, is_8996 = 0, is_660 = 0;
 	size_t num_clks, i;
 	struct clk_hw **hw_clks;
 	const struct rpm_smd_clk_desc *desc;
 
 	is_8996 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,rpmcc-msm8996");
-	is_falcon = of_device_is_compatible(pdev->dev.of_node,
-						"qcom,rpmcc-msmfalcon");
+	is_660 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,rpmcc-sdm660");
 	if (is_8996) {
 		ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
-	} else if (is_falcon) {
-		ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX);
+	} else if (is_660) {
+		ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
 	}
@@ -849,8 +849,8 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 		clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);
 
 		clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk);
-	} else if (is_falcon) {
-		clk_prepare_enable(msmfalcon_cxo_a.hw.clk);
+	} else if (is_660) {
+		clk_prepare_enable(sdm660_cxo_a.hw.clk);
 
 		/* Hold an active set vote for the cnoc_periph resource */
 		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);
diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-sdm660.c
index 1e1c871ef22c..da4c6e8797d7 100644
--- a/drivers/clk/qcom/gcc-msmfalcon.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -23,7 +23,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap.h"
 #include "clk-rcg.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -2580,7 +2580,7 @@ static struct clk_fixed_factor gcc_ce1_axi_m_clk = {
 	},
 };
 
-struct clk_hw *gcc_msmfalcon_hws[] = {
+struct clk_hw *gcc_sdm660_hws[] = {
 	[GCC_XO] =      &xo.hw,
 	[GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw,
 	[GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw,
@@ -2588,7 +2588,7 @@ struct clk_hw *gcc_msmfalcon_hws[] = {
 	[GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw,
 };
 
-static struct clk_regmap *gcc_falcon_clocks[] = {
+static struct clk_regmap *gcc_660_clocks[] = {
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
 	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
 	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
@@ -2728,7 +2728,7 @@ static struct clk_regmap *gcc_falcon_clocks[] = {
 					&hlos2_vote_turing_adsp_smmu_clk.clkr,
 };
 
-static const struct qcom_reset_map gcc_falcon_resets[] = {
+static const struct qcom_reset_map gcc_660_resets[] = {
 	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
 	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
 	[GCC_UFS_BCR] = { 0x75000 },
@@ -2740,7 +2740,7 @@ static const struct qcom_reset_map gcc_falcon_resets[] = {
 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
-static const struct regmap_config gcc_falcon_regmap_config = {
+static const struct regmap_config gcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2748,28 +2748,28 @@ static const struct regmap_config gcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gcc_falcon_desc = {
-	.config = &gcc_falcon_regmap_config,
-	.clks = gcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gcc_falcon_clocks),
-	.hwclks = gcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws),
-	.resets = gcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(gcc_falcon_resets),
+static const struct qcom_cc_desc gcc_660_desc = {
+	.config = &gcc_660_regmap_config,
+	.clks = gcc_660_clocks,
+	.num_clks = ARRAY_SIZE(gcc_660_clocks),
+	.hwclks = gcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(gcc_sdm660_hws),
+	.resets = gcc_660_resets,
+	.num_resets = ARRAY_SIZE(gcc_660_resets),
 };
 
-static const struct of_device_id gcc_falcon_match_table[] = {
-	{ .compatible = "qcom,gcc-msmfalcon" },
+static const struct of_device_id gcc_660_match_table[] = {
+	{ .compatible = "qcom,gcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
 
-static int gcc_falcon_probe(struct platform_device *pdev)
+static int gcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &gcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -2795,7 +2795,7 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 		return PTR_ERR(vdd_dig_ao.regulator[0]);
 	}
 
-	ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GCC clocks\n");
 		return ret;
@@ -2816,25 +2816,25 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gcc_falcon_driver = {
-	.probe		= gcc_falcon_probe,
+static struct platform_driver gcc_660_driver = {
+	.probe		= gcc_660_probe,
 	.driver		= {
-		.name	= "gcc-msmfalcon",
-		.of_match_table = gcc_falcon_match_table,
+		.name	= "gcc-sdm660",
+		.of_match_table = gcc_660_match_table,
 	},
 };
 
-static int __init gcc_falcon_init(void)
+static int __init gcc_660_init(void)
 {
-	return platform_driver_register(&gcc_falcon_driver);
+	return platform_driver_register(&gcc_660_driver);
 }
-core_initcall_sync(gcc_falcon_init);
+core_initcall_sync(gcc_660_init);
 
-static void __exit gcc_falcon_exit(void)
+static void __exit gcc_660_exit(void)
 {
-	platform_driver_unregister(&gcc_falcon_driver);
+	platform_driver_unregister(&gcc_660_driver);
 }
-module_exit(gcc_falcon_exit);
+module_exit(gcc_660_exit);
 
 /* Debug Mux for measure */
 static struct measure_clk_data debug_mux_priv = {
@@ -3210,11 +3210,11 @@ static struct clk_debug_mux gcc_debug_mux = {
 };
 
 static const struct of_device_id clk_debug_match_table[] = {
-	{ .compatible = "qcom,gcc-debug-msmfalcon" },
+	{ .compatible = "qcom,gcc-debug-sdm660" },
 	{}
 };
 
-static int clk_debug_falcon_probe(struct platform_device *pdev)
+static int clk_debug_660_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct clk *clk;
@@ -3307,16 +3307,16 @@ static int clk_debug_falcon_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver clk_debug_driver = {
-	.probe = clk_debug_falcon_probe,
+	.probe = clk_debug_660_probe,
 	.driver = {
-		.name = "gcc-debug-msmfalcon",
+		.name = "gcc-debug-sdm660",
 		.of_match_table = clk_debug_match_table,
 		.owner = THIS_MODULE,
 	},
 };
 
-int __init clk_debug_falcon_init(void)
+int __init clk_debug_660_init(void)
 {
 	return platform_driver_register(&clk_debug_driver);
 }
-fs_initcall(clk_debug_falcon_init);
+fs_initcall(clk_debug_660_init);
diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-sdm660.c
index 9b7dd907a6f3..b16b17451c76 100644
--- a/drivers/clk/qcom/gpucc-msmfalcon.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -22,7 +22,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "common.h"
@@ -30,7 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }
@@ -316,7 +316,7 @@ static struct clk_branch gpucc_rbcpr_clk = {
 	},
 };
 
-static struct clk_regmap *gpucc_falcon_clocks[] = {
+static struct clk_regmap *gpucc_660_clocks[] = {
 	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
 	[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
 	[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
@@ -328,7 +328,7 @@ static struct clk_regmap *gpucc_falcon_clocks[] = {
 	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
 };
 
-static const struct regmap_config gpucc_falcon_regmap_config = {
+static const struct regmap_config gpucc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -336,18 +336,18 @@ static const struct regmap_config gpucc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gpucc_falcon_desc = {
-	.config = &gpucc_falcon_regmap_config,
-	.clks = gpucc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gpucc_falcon_clocks),
+static const struct qcom_cc_desc gpucc_660_desc = {
+	.config = &gpucc_660_regmap_config,
+	.clks = gpucc_660_clocks,
+	.num_clks = ARRAY_SIZE(gpucc_660_clocks),
 };
 
-static const struct of_device_id gpucc_falcon_match_table[] = {
-	{ .compatible = "qcom,gpucc-msmfalcon" },
+static const struct of_device_id gpucc_660_match_table[] = {
+	{ .compatible = "qcom,gpucc-sdm660" },
 	{ .compatible = "qcom,gpucc-msmtriton" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gpucc_660_match_table);
 
 static int of_get_fmax_vdd_class(struct platform_device *pdev,
 		struct clk_hw *hw, char *prop_name, u32 index)
@@ -407,13 +407,13 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev,
 	return 0;
 }
 
-static int gpucc_falcon_probe(struct platform_device *pdev)
+static int gpucc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 	bool is_triton = 0;
 
-	regmap = qcom_cc_map(pdev, &gpucc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gpucc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -464,7 +464,7 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap,
 							&gpu_pll0_config);
 
-	ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
 		return ret;
@@ -477,22 +477,22 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gpucc_falcon_driver = {
-	.probe		= gpucc_falcon_probe,
+static struct platform_driver gpucc_660_driver = {
+	.probe		= gpucc_660_probe,
 	.driver		= {
-		.name	= "gpucc-msmfalcon",
-		.of_match_table = gpucc_falcon_match_table,
+		.name	= "gpucc-sdm660",
+		.of_match_table = gpucc_660_match_table,
 	},
 };
 
-static int __init gpucc_falcon_init(void)
+static int __init gpucc_660_init(void)
 {
-	return platform_driver_register(&gpucc_falcon_driver);
+	return platform_driver_register(&gpucc_660_driver);
 }
-core_initcall_sync(gpucc_falcon_init);
+core_initcall_sync(gpucc_660_init);
 
-static void __exit gpucc_falcon_exit(void)
+static void __exit gpucc_660_exit(void)
 {
-	platform_driver_unregister(&gpucc_falcon_driver);
+	platform_driver_unregister(&gpucc_660_driver);
 }
-module_exit(gpucc_falcon_exit);
+module_exit(gpucc_660_exit);
diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c
index b51ab4f21561..f356be38a25c 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.c
+++ b/drivers/clk/qcom/mdss/mdss-pll.c
@@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
 		pll_res->target_id = MDSS_PLL_TARGET_8996;
 		pll_res->revision = 2;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) {
+	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
-		pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON;
+		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
 		pll_res->revision = 2;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8998;
@@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
 	{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
 	{.compatible = "qcom,mdss_dp_pll_8998"},
 	{.compatible = "qcom,mdss_hdmi_pll_8998"},
-	{.compatible = "qcom,mdss_dsi_pll_msmfalcon"},
+	{.compatible = "qcom,mdss_dsi_pll_sdm660"},
 	{}
 };
 
diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h
index 01664eaa815c..e0e62a0f379b 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.h
+++ b/drivers/clk/qcom/mdss/mdss-pll.h
@@ -51,7 +51,7 @@ enum {
 
 enum {
 	MDSS_PLL_TARGET_8996,
-	MDSS_PLL_TARGET_MSMFALCON,
+	MDSS_PLL_TARGET_SDM660,
 };
 
 #define DFPS_MAX_NUM_OF_FRAME_RATES 20
diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-sdm660.c
index 59dbebd825fd..daece455454c 100644
--- a/drivers/clk/qcom/mmcc-msmfalcon.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -21,7 +21,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap-divider.h"
 #include "clk-voter.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \
@@ -2816,12 +2816,12 @@ static struct clk_branch mmss_video_subcore0_clk = {
 	},
 };
 
-struct clk_hw *mmcc_msmfalcon_hws[] = {
+struct clk_hw *mmcc_sdm660_hws[] = {
 	[MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw,
 	[MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw,
 };
 
-static struct clk_regmap *mmcc_falcon_clocks[] = {
+static struct clk_regmap *mmcc_660_clocks[] = {
 	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
 	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
 	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
@@ -2954,11 +2954,11 @@ static struct clk_regmap *mmcc_falcon_clocks[] = {
 	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
 };
 
-static const struct qcom_reset_map mmcc_falcon_resets[] = {
+static const struct qcom_reset_map mmcc_660_resets[] = {
 	[CAMSS_MICRO_BCR] = { 0x3490 },
 };
 
-static const struct regmap_config mmcc_falcon_regmap_config = {
+static const struct regmap_config mmcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2966,28 +2966,28 @@ static const struct regmap_config mmcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc mmcc_falcon_desc = {
-	.config = &mmcc_falcon_regmap_config,
-	.clks = mmcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(mmcc_falcon_clocks),
-	.hwclks = mmcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws),
-	.resets = mmcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(mmcc_falcon_resets),
+static const struct qcom_cc_desc mmcc_660_desc = {
+	.config = &mmcc_660_regmap_config,
+	.clks = mmcc_660_clocks,
+	.num_clks = ARRAY_SIZE(mmcc_660_clocks),
+	.hwclks = mmcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws),
+	.resets = mmcc_660_resets,
+	.num_resets = ARRAY_SIZE(mmcc_660_resets),
 };
 
-static const struct of_device_id mmcc_falcon_match_table[] = {
-	{ .compatible = "qcom,mmcc-msmfalcon" },
+static const struct of_device_id mmcc_660_match_table[] = {
+	{ .compatible = "qcom,mmcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
 
-static int mmcc_falcon_probe(struct platform_device *pdev)
+static int mmcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &mmcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &mmcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -3024,7 +3024,7 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config);
 	clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config);
 
-	ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register MMSS clocks\n");
 		return ret;
@@ -3035,22 +3035,22 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver mmcc_falcon_driver = {
-	.probe		= mmcc_falcon_probe,
+static struct platform_driver mmcc_660_driver = {
+	.probe		= mmcc_660_probe,
 	.driver		= {
-		.name	= "mmcc-msmfalcon",
-		.of_match_table = mmcc_falcon_match_table,
+		.name	= "mmcc-sdm660",
+		.of_match_table = mmcc_660_match_table,
 	},
 };
 
-static int __init mmcc_falcon_init(void)
+static int __init mmcc_660_init(void)
 {
-	return platform_driver_register(&mmcc_falcon_driver);
+	return platform_driver_register(&mmcc_660_driver);
 }
-core_initcall_sync(mmcc_falcon_init);
+core_initcall_sync(mmcc_660_init);
 
-static void __exit mmcc_falcon_exit(void)
+static void __exit mmcc_660_exit(void)
 {
-	platform_driver_unregister(&mmcc_falcon_driver);
+	platform_driver_unregister(&mmcc_660_driver);
 }
-module_exit(mmcc_falcon_exit);
+module_exit(mmcc_660_exit);
diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-660.h
index 75567dbe2329..f98a96033ea9 100644
--- a/drivers/clk/qcom/vdd-level-falcon.h
+++ b/drivers/clk/qcom/vdd-level-660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
-#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
+#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
+#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
 
 #include <linux/regulator/rpm-smd-regulator.h>
 #include <linux/regulator/consumer.h>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 11d88df37d31..d45df18a7019 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO
 
 config CRYPTO_DEV_QCOM_MSM_QCE
         tristate "Qualcomm Crypto Engine (QCE) module"
-        select  CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON
+        select  CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_MSMTRITON
         default n
         help
           This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
           MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900,
-		  MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON.
+		  MSMTITANINUM, APQ8084, MSM8998, SDM660 and MSMTRITON.
 
           To compile this driver as a module, choose M here: the
           For MSM7x30 MSM8660 and MSM8x55 the module is called qce
           For MSM8960, APQ8064 and MSM9615 the module is called qce40
           For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM,
-		  APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50.
+		  APQ8084, MSM8998, SDM660 and MSMTRITON the module is called qce50.
 
 config CRYPTO_DEV_QCEDEV
         tristate "QCEDEV Interface to CE module"
@@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV
         help
           This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
           MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996,
-          APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the
+          APQ8084, MSM8998, SDM660, MSMTRITON. This exposes the
           interface to the QCE hardware accelerator via IOCTLs.
 
           To compile this driver as a module, choose M here: the
diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c
index 674ca6161af9..aa59677c4b6a 100644
--- a/drivers/leds/leds-qpnp-flash-v2.c
+++ b/drivers/leds/leds-qpnp-flash-v2.c
@@ -1733,7 +1733,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led,
 	led->pdata->thermal_hysteresis = -EINVAL;
 	rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val);
 	if (!rc) {
-		if (led->pdata->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			val = THERMAL_HYST_TEMP_TO_VAL(val, 20);
 		else
 			val = THERMAL_HYST_TEMP_TO_VAL(val, 15);
diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c
index 56750ac8e9e2..718badb16ea1 100644
--- a/drivers/leds/leds-qpnp-wled.c
+++ b/drivers/leds/leds-qpnp-wled.c
@@ -479,7 +479,7 @@ static int qpnp_wled_swire_avdd_config(struct qpnp_wled *wled)
 	u8 val;
 
 	if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE &&
-		wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE)
 		return 0;
 
 	if (!wled->disp_type_amoled || wled->avdd_mode_spmi)
@@ -1103,11 +1103,11 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled)
 	u8 reg = 0;
 
 	/*
-	 * AVDD trim adjustment is not required for pmi8998/pm2falcon and not
+	 * AVDD trim adjustment is not required for pmi8998/pm660l and not
 	 * supported for pmi8994.
 	 */
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE ||
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE ||
 		wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE)
 		return false;
 
@@ -1133,7 +1133,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled)
 
 	/* Configure the LOOP COMP GM register */
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		if (wled->loop_auto_gm_en)
 			reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN;
 
@@ -1179,7 +1179,7 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled)
 		return 0;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		ovp_table = qpnp_wled_ovp_thresholds_pmi8998;
 	else
 		ovp_table = qpnp_wled_ovp_thresholds_pmi8994;
@@ -1264,10 +1264,10 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled)
 
 	/*
 	 * At present, configuring the mode to SPMI/SWIRE for controlling
-	 * AVDD voltage is available only in pmi8998/pm2falcon.
+	 * AVDD voltage is available only in pmi8998/pm660l.
 	 */
 	if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE &&
-		wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE)
 		return 0;
 
 	/* AMOLED_VOUT should be configured for AMOLED */
@@ -1313,7 +1313,7 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled)
 		wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		ilim_table = qpnp_wled_ilim_settings_pmi8998;
 		if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA)
 			wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA;
@@ -1352,7 +1352,7 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled)
 	u8 reg = 0;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		vref_setting = vref_setting_pmi8998;
 	else
 		vref_setting = vref_setting_pmi8994;
@@ -1420,7 +1420,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
 
 	/* Configure auto PFM mode for LCD mode only */
 	if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		&& !wled->disp_type_amoled) {
 		reg = 0;
 		reg |= wled->lcd_auto_pfm_thresh;
@@ -1563,7 +1563,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
 		reg = QPNP_WLED_SINK_TEST5_DIG;
 	} else {
 		reg = QPNP_WLED_SINK_TEST5_HYB;
-		if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		if (wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT;
 	}
 
@@ -1816,7 +1816,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 
 	if (wled->disp_type_amoled) {
 		if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			wled->loop_ea_gm =
 				QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998;
 		else
@@ -1836,7 +1836,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		wled->loop_auto_gm_en =
 			of_property_read_bool(pdev->dev.of_node,
 					"qcom,loop-auto-gm-en");
@@ -1852,7 +1852,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 
 		if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4)
 			wled->lcd_auto_pfm_en = false;
@@ -1905,7 +1905,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		wled->vref_uv = vref_setting_pmi8998.default_uv;
 	else
 		wled->vref_uv = vref_setting_pmi8994.default_uv;
@@ -1929,7 +1929,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		wled->ovp_mv = 29600;
 	else
 		wled->ovp_mv = 29500;
@@ -1943,7 +1943,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		if (wled->disp_type_amoled)
 			wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA;
 		else
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 223339ff119d..e1ef353aa1e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -46,7 +46,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-14nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qrbtc-v2.o
-obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3-falcon.o
+obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3-660.o
 obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCMSTB_SATA)		+= phy-brcmstb-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c
index e88c00e01e0b..a0cb7d0896d1 100644
--- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c
+++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c
@@ -12,12 +12,12 @@
  *
  */
 
-#include "phy-qcom-ufs-qmp-v3-falcon.h"
+#include "phy-qcom-ufs-qmp-v3-660.h"
 
-#define UFS_PHY_NAME "ufs_phy_qmp_v3_falcon"
+#define UFS_PHY_NAME "ufs_phy_qmp_v3_660"
 
 static
-int ufs_qcom_phy_qmp_v3_falcon_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
+int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
 					bool is_rate_B)
 {
 	int err;
@@ -55,9 +55,9 @@ out:
 	return err;
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_init(struct phy *generic_phy)
+static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy)
 {
-	struct ufs_qcom_phy_qmp_v3_falcon *phy = phy_get_drvdata(generic_phy);
+	struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy);
 	struct ufs_qcom_phy *phy_common = &phy->common_cfg;
 	int err;
 
@@ -80,7 +80,7 @@ out:
 }
 
 static
-void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy,
 					 bool power_ctrl)
 {
 	if (!power_ctrl) {
@@ -104,7 +104,7 @@ void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy,
 }
 
 static inline
-void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy,
 						   u32 val)
 {
 	/*
@@ -114,7 +114,7 @@ void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy,
 }
 
 static
-void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
 						bool ctrl)
 {
 	u32 temp;
@@ -131,7 +131,7 @@ void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
 	mb();
 }
 
-static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes(
+static inline void ufs_qcom_phy_qmp_v3_660_start_serdes(
 					struct ufs_qcom_phy *phy)
 {
 	u32 tmp;
@@ -144,7 +144,7 @@ static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes(
 	mb();
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready(
+static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready(
 				struct ufs_qcom_phy *phy_common)
 {
 	int err = 0;
@@ -158,7 +158,7 @@ static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready(
 	return err;
 }
 
-static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump(
+static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump(
 					struct ufs_qcom_phy *phy)
 {
 	ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
@@ -171,30 +171,30 @@ static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump(
 					"PHY TX0 Registers ");
 }
 
-struct phy_ops ufs_qcom_phy_qmp_v3_falcon_phy_ops = {
-	.init		= ufs_qcom_phy_qmp_v3_falcon_init,
+struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = {
+	.init		= ufs_qcom_phy_qmp_v3_660_init,
 	.exit		= ufs_qcom_phy_exit,
 	.power_on	= ufs_qcom_phy_power_on,
 	.power_off	= ufs_qcom_phy_power_off,
 	.owner		= THIS_MODULE,
 };
 
-struct ufs_qcom_phy_specific_ops phy_v3_falcon_ops = {
-	.calibrate_phy		= ufs_qcom_phy_qmp_v3_falcon_phy_calibrate,
-	.start_serdes		= ufs_qcom_phy_qmp_v3_falcon_start_serdes,
+struct ufs_qcom_phy_specific_ops phy_v3_660_ops = {
+	.calibrate_phy		= ufs_qcom_phy_qmp_v3_660_phy_calibrate,
+	.start_serdes		= ufs_qcom_phy_qmp_v3_660_start_serdes,
 	.is_physical_coding_sublayer_ready =
-				ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready,
-	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable,
-	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg,
-	.power_control		= ufs_qcom_phy_qmp_v3_falcon_power_control,
-	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump,
+				ufs_qcom_phy_qmp_v3_660_is_pcs_ready,
+	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable,
+	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg,
+	.power_control		= ufs_qcom_phy_qmp_v3_660_power_control,
+	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_660_dbg_register_dump,
 };
 
-static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev)
+static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct phy *generic_phy;
-	struct ufs_qcom_phy_qmp_v3_falcon *phy;
+	struct ufs_qcom_phy_qmp_v3_660 *phy;
 	int err = 0;
 
 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
@@ -204,8 +204,8 @@ static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev)
 	}
 
 	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
-				&ufs_qcom_phy_qmp_v3_falcon_phy_ops,
-				&phy_v3_falcon_ops);
+				&ufs_qcom_phy_qmp_v3_660_phy_ops,
+				&phy_v3_660_ops);
 
 	if (!generic_phy) {
 		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
@@ -223,7 +223,7 @@ out:
 	return err;
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev)
+static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct phy *generic_phy = to_phy(dev);
@@ -238,23 +238,23 @@ static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev)
 	return err;
 }
 
-static const struct of_device_id ufs_qcom_phy_qmp_v3_falcon_of_match[] = {
-	{.compatible = "qcom,ufs-phy-qmp-v3-falcon"},
+static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = {
+	{.compatible = "qcom,ufs-phy-qmp-v3-660"},
 	{},
 };
-MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_falcon_of_match);
+MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match);
 
-static struct platform_driver ufs_qcom_phy_qmp_v3_falcon_driver = {
-	.probe = ufs_qcom_phy_qmp_v3_falcon_probe,
-	.remove = ufs_qcom_phy_qmp_v3_falcon_remove,
+static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = {
+	.probe = ufs_qcom_phy_qmp_v3_660_probe,
+	.remove = ufs_qcom_phy_qmp_v3_660_remove,
 	.driver = {
-		.of_match_table = ufs_qcom_phy_qmp_v3_falcon_of_match,
-		.name = "ufs_qcom_phy_qmp_v3_falcon",
+		.of_match_table = ufs_qcom_phy_qmp_v3_660_of_match,
+		.name = "ufs_qcom_phy_qmp_v3_660",
 		.owner = THIS_MODULE,
 	},
 };
 
-module_platform_driver(ufs_qcom_phy_qmp_v3_falcon_driver);
+module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver);
 
-MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 falcon");
+MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h
index e64601cc6b22..8d0183d87e20 100644
--- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h
+++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h
@@ -12,8 +12,8 @@
  *
  */
 
-#ifndef UFS_QCOM_PHY_QMP_V3_FALCON_H_
-#define UFS_QCOM_PHY_QMP_V3_FALCON_H_
+#ifndef UFS_QCOM_PHY_QMP_V3_660_H_
+#define UFS_QCOM_PHY_QMP_V3_660_H_
 
 #include "phy-qcom-ufs-i.h"
 
@@ -185,14 +185,14 @@
 #define UFS_PHY_RX_LINECFG_DISABLE_BIT		BIT(1)
 
 /*
- * This structure represents the v3 falcon specific phy.
+ * This structure represents the v3 660 specific phy.
  * common_cfg MUST remain the first field in this structure
  * in case extra fields are added. This way, when calling
  * get_ufs_qcom_phy() of generic phy, we can extract the
  * common phy structure (struct ufs_qcom_phy) out of it
  * regardless of the relevant specific phy.
  */
-struct ufs_qcom_phy_qmp_v3_falcon {
+struct ufs_qcom_phy_qmp_v3_660 {
 	struct ufs_qcom_phy common_cfg;
 };
 
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 68546eec7f61..3f9f58f57393 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -112,13 +112,13 @@ config PINCTRL_MSM8996
 	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
 	  Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
 
-config PINCTRL_MSMFALCON
-	tristate "Qualcomm MSMFALCON pin controller driver"
+config PINCTRL_SDM660
+	tristate "Qualcomm SDM660 pin controller driver"
 	depends on GPIOLIB && OF
 	select PINCTRL_MSM
 	help
 	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
-	  Qualcomm TLMM block found in the Qualcomm MSMFALCON platform.
+	  Qualcomm TLMM block found in the Qualcomm SDM660 platform.
 
 config PINCTRL_WCD
 	tristate "Qualcomm Technologies, Inc WCD pin controller driver"
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index fa228c7243e2..502b91f455d7 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -14,6 +14,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
 obj-$(CONFIG_PINCTRL_MSM8996)	+= pinctrl-msm8996.o
 obj-$(CONFIG_PINCTRL_MSM8998)	+= pinctrl-msm8998.o
-obj-$(CONFIG_PINCTRL_MSMFALCON)	+= pinctrl-msmfalcon.o
+obj-$(CONFIG_PINCTRL_SDM660)	+= pinctrl-sdm660.o
 obj-$(CONFIG_PINCTRL_WCD)	+= pinctrl-wcd.o
 obj-$(CONFIG_PINCTRL_LPI)	+= pinctrl-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c
index 91bbce2ce1d1..4dbb4cae2fae 100644
--- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -92,7 +92,7 @@
 		.intr_detection_bit = -1,		\
 		.intr_detection_width = -1,		\
 	}
-static const struct pinctrl_pin_desc msmfalcon_pins[] = {
+static const struct pinctrl_pin_desc sdm660_pins[] = {
 	PINCTRL_PIN(0, "GPIO_0"),
 	PINCTRL_PIN(1, "GPIO_1"),
 	PINCTRL_PIN(2, "GPIO_2"),
@@ -341,7 +341,7 @@ static const unsigned int sdc2_cmd_pins[] = { 118 };
 static const unsigned int sdc2_data_pins[] = { 119 };
 static const unsigned int sdc1_rclk_pins[] = { 120 };
 
-enum msmfalcon_functions {
+enum sdm660_functions {
 	msm_mux_blsp_spi1,
 	msm_mux_gpio,
 	msm_mux_blsp_uim1,
@@ -1259,7 +1259,7 @@ static const char * const LCD_PWR_groups[] = {
 	"gpio113",
 };
 
-static const struct msm_function msmfalcon_functions[] = {
+static const struct msm_function sdm660_functions[] = {
 	FUNCTION(blsp_spi1),
 	FUNCTION(gpio),
 	FUNCTION(blsp_uim1),
@@ -1486,7 +1486,7 @@ static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(LCD_PWR),
 };
 
-static const struct msm_pingroup msmfalcon_groups[] = {
+static const struct msm_pingroup sdm660_groups[] = {
 	PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA,
 		 qdss_gpio4, atest_gpsadc1, NA),
 	PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA,
@@ -1675,48 +1675,48 @@ static const struct msm_pingroup msmfalcon_groups[] = {
 	SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0),
 };
 
-static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = {
-	.pins = msmfalcon_pins,
-	.npins = ARRAY_SIZE(msmfalcon_pins),
-	.functions = msmfalcon_functions,
-	.nfunctions = ARRAY_SIZE(msmfalcon_functions),
-	.groups = msmfalcon_groups,
-	.ngroups = ARRAY_SIZE(msmfalcon_groups),
+static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
+	.pins = sdm660_pins,
+	.npins = ARRAY_SIZE(sdm660_pins),
+	.functions = sdm660_functions,
+	.nfunctions = ARRAY_SIZE(sdm660_functions),
+	.groups = sdm660_groups,
+	.ngroups = ARRAY_SIZE(sdm660_groups),
 	.ngpios = 114,
 };
 
-static int msmfalcon_pinctrl_probe(struct platform_device *pdev)
+static int sdm660_pinctrl_probe(struct platform_device *pdev)
 {
-	return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl);
+	return msm_pinctrl_probe(pdev, &sdm660_pinctrl);
 }
 
-static const struct of_device_id msmfalcon_pinctrl_of_match[] = {
-	{ .compatible = "qcom,msmfalcon-pinctrl", },
+static const struct of_device_id sdm660_pinctrl_of_match[] = {
+	{ .compatible = "qcom,sdm660-pinctrl", },
 	{ },
 };
 
-static struct platform_driver msmfalcon_pinctrl_driver = {
+static struct platform_driver sdm660_pinctrl_driver = {
 	.driver = {
-		.name = "msmfalcon-pinctrl",
+		.name = "sdm660-pinctrl",
 		.owner = THIS_MODULE,
-		.of_match_table = msmfalcon_pinctrl_of_match,
+		.of_match_table = sdm660_pinctrl_of_match,
 	},
-	.probe = msmfalcon_pinctrl_probe,
+	.probe = sdm660_pinctrl_probe,
 	.remove = msm_pinctrl_remove,
 };
 
-static int __init msmfalcon_pinctrl_init(void)
+static int __init sdm660_pinctrl_init(void)
 {
-	return platform_driver_register(&msmfalcon_pinctrl_driver);
+	return platform_driver_register(&sdm660_pinctrl_driver);
 }
-arch_initcall(msmfalcon_pinctrl_init);
+arch_initcall(sdm660_pinctrl_init);
 
-static void __exit msmfalcon_pinctrl_exit(void)
+static void __exit sdm660_pinctrl_exit(void)
 {
-	platform_driver_unregister(&msmfalcon_pinctrl_driver);
+	platform_driver_unregister(&sdm660_pinctrl_driver);
 }
-module_exit(msmfalcon_pinctrl_exit);
+module_exit(sdm660_pinctrl_exit);
 
-MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver");
+MODULE_DESCRIPTION("QTI sdm660 pinctrl driver");
 MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match);
+MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match);
diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c
index cfc8093fa3dd..6b5db58f856a 100644
--- a/drivers/platform/msm/qpnp-revid.c
+++ b/drivers/platform/msm/qpnp-revid.c
@@ -56,8 +56,8 @@ static const char *const pmic_names[] = {
 	[PMI8998_SUBTYPE] = "PMI8998",
 	[PM8005_SUBTYPE] = "PM8005",
 	[PM8937_SUBTYPE] = "PM8937",
-	[PM2FALCON_SUBTYPE] = "PM2FALCON",
-	[PMFALCON_SUBTYPE] = "PMFALCON",
+	[PM660L_SUBTYPE] = "PM660L",
+	[PM660_SUBTYPE] = "PM660",
 	[PMI8937_SUBTYPE] = "PMI8937",
 };
 
diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c
index 7c1ece431beb..edd9b9ff28cf 100644
--- a/drivers/power/qcom-charger/qpnp-fg-gen3.c
+++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c
@@ -3157,7 +3157,7 @@ static int fg_parse_dt(struct fg_chip *chip)
 			return -EINVAL;
 		}
 		break;
-	case PMFALCON_SUBTYPE:
+	case PM660_SUBTYPE:
 		chip->sp = pmi8998_v2_sram_params;
 		chip->alg_flags = pmi8998_v2_alg_flags;
 		break;
diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c
index 90e3689086a6..463cbb7cb8ba 100644
--- a/drivers/power/qcom-charger/qpnp-smb2.c
+++ b/drivers/power/qcom-charger/qpnp-smb2.c
@@ -1453,7 +1453,7 @@ static int smb2_setup_wa_flags(struct smb2 *chip)
 		if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */
 			chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT;
 		break;
-	case PMFALCON_SUBTYPE:
+	case PM660_SUBTYPE:
 		chip->chg.wa_flags |= BOOST_BACK_WA;
 		break;
 	default:
diff --git a/drivers/regulator/cpr4-mmss-ldo-regulator.c b/drivers/regulator/cpr4-mmss-ldo-regulator.c
index 9fa5c309b02a..69c11a9e5da2 100644
--- a/drivers/regulator/cpr4-mmss-ldo-regulator.c
+++ b/drivers/regulator/cpr4-mmss-ldo-regulator.c
@@ -36,10 +36,10 @@
 
 #include "cpr3-regulator.h"
 
-#define MSMFALCON_MMSS_FUSE_CORNERS	6
+#define SDM660_MMSS_FUSE_CORNERS	6
 
 /**
- * struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON
+ * struct cpr4_sdm660_mmss_fuses - MMSS specific fuse data for SDM660
  * @init_voltage:	Initial (i.e. open-loop) voltage fuse parameter value
  *			for each fuse corner (raw, not converted to a voltage)
  * @offset_voltage:	The closed-loop voltage margin adjustment fuse parameter
@@ -55,19 +55,19 @@
  *
  * This struct holds the values for all of the fuses read from memory.
  */
-struct cpr4_msmfalcon_mmss_fuses {
-	u64	init_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
-	u64	offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
+struct cpr4_sdm660_mmss_fuses {
+	u64	init_voltage[SDM660_MMSS_FUSE_CORNERS];
+	u64	offset_voltage[SDM660_MMSS_FUSE_CORNERS];
 	u64	cpr_fusing_rev;
-	u64	ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS];
+	u64	ldo_enable[SDM660_MMSS_FUSE_CORNERS];
 	u64	ldo_cpr_cl_enable;
 };
 
 /* Fuse combos 0 -  7 map to CPR fusing revision 0 - 7 */
-#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT	8
+#define CPR4_SDM660_MMSS_FUSE_COMBO_COUNT	8
 
 /*
- * MSMFALCON MMSS fuse parameter locations:
+ * SDM660 MMSS fuse parameter locations:
  *
  * Structs are organized with the following dimensions:
  *	Outer: 0 to 3 for fuse corners from lowest to highest corner
@@ -79,7 +79,7 @@ struct cpr4_msmfalcon_mmss_fuses {
  *		a given parameter may correspond to different fuse rows.
  */
 static const struct cpr3_fuse_param
-msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_init_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{65, 39, 43}, {} },
 	{{65, 39, 43}, {} },
 	{{65, 34, 38}, {} },
@@ -88,13 +88,13 @@ msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 	{{65, 24, 28}, {} },
 };
 
-static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = {
+static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = {
 	{71, 34, 36},
 	{},
 };
 
 static const struct cpr3_fuse_param
-msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_offset_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{} },
 	{{} },
 	{{} },
@@ -104,7 +104,7 @@ msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 };
 
 static const struct cpr3_fuse_param
-msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_ldo_enable_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{73, 62, 62}, {} },
 	{{73, 61, 61}, {} },
 	{{73, 60, 60}, {} },
@@ -113,15 +113,15 @@ msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 	{{73, 57, 57}, {} },
 };
 
-static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = {
+static const struct cpr3_fuse_param sdm660_ldo_cpr_cl_enable_param[] = {
 	{71, 38, 38},
 	{},
 };
 
-/* Additional MSMFALCON specific data: */
+/* Additional SDM660 specific data: */
 
 /* Open loop voltage fuse reference voltages in microvolts */
-static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = {
+static const int sdm660_mmss_fuse_ref_volt[SDM660_MMSS_FUSE_CORNERS] = {
 	584000,
 	644000,
 	724000,
@@ -130,36 +130,36 @@ static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = {
 	924000,
 };
 
-#define MSMFALCON_MMSS_FUSE_STEP_VOLT		10000
-#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT	10000
-#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE	5
+#define SDM660_MMSS_FUSE_STEP_VOLT		10000
+#define SDM660_MMSS_OFFSET_FUSE_STEP_VOLT	10000
+#define SDM660_MMSS_VOLTAGE_FUSE_SIZE	5
 
-#define MSMFALCON_MMSS_CPR_SENSOR_COUNT		11
+#define SDM660_MMSS_CPR_SENSOR_COUNT		11
 
-#define MSMFALCON_MMSS_CPR_CLOCK_RATE		19200000
+#define SDM660_MMSS_CPR_CLOCK_RATE		19200000
 
 /**
- * cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter
+ * cpr4_sdm660_mmss_read_fuse_data() - load MMSS specific fuse parameter
  *		values
  * @vreg:		Pointer to the CPR3 regulator
  *
- * This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with
+ * This function allocates a cpr4_sdm660_mmss_fuses struct, fills it with
  * values read out of hardware fuses, and finally copies common fuse values
  * into the regulator struct.
  *
  * Return: 0 on success, errno on failure
  */
-static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
+static int cpr4_sdm660_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 {
 	void __iomem *base = vreg->thread->ctrl->fuse_base;
-	struct cpr4_msmfalcon_mmss_fuses *fuse;
+	struct cpr4_sdm660_mmss_fuses *fuse;
 	int i, rc;
 
 	fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
 	if (!fuse)
 		return -ENOMEM;
 
-	rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param,
+	rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param,
 			&fuse->cpr_fusing_rev);
 	if (rc) {
 		cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n",
@@ -168,7 +168,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 	}
 	cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev);
 
-	rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param,
+	rc = cpr3_read_fuse_param(base, sdm660_ldo_cpr_cl_enable_param,
 			&fuse->ldo_cpr_cl_enable);
 	if (rc) {
 		cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n",
@@ -176,9 +176,9 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		return rc;
 	}
 
-	for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) {
+	for (i = 0; i < SDM660_MMSS_FUSE_CORNERS; i++) {
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_init_voltage_param[i],
+			sdm660_mmss_init_voltage_param[i],
 			&fuse->init_voltage[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
@@ -187,7 +187,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		}
 
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_offset_voltage_param[i],
+			sdm660_mmss_offset_voltage_param[i],
 			&fuse->offset_voltage[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n",
@@ -196,7 +196,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		}
 
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_ldo_enable_param[i],
+			sdm660_mmss_ldo_enable_param[i],
 			&fuse->ldo_enable[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n",
@@ -206,31 +206,31 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 	}
 
 	vreg->fuse_combo = fuse->cpr_fusing_rev;
-	if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) {
+	if (vreg->fuse_combo >= CPR4_SDM660_MMSS_FUSE_COMBO_COUNT) {
 		cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n",
 			vreg->fuse_combo,
-			CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1);
+			CPR4_SDM660_MMSS_FUSE_COMBO_COUNT - 1);
 		return -EINVAL;
 	}
 
 	vreg->cpr_rev_fuse	= fuse->cpr_fusing_rev;
-	vreg->fuse_corner_count	= MSMFALCON_MMSS_FUSE_CORNERS;
+	vreg->fuse_corner_count	= SDM660_MMSS_FUSE_CORNERS;
 	vreg->platform_fuses	= fuse;
 
 	return 0;
 }
 
 /**
- * cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop
+ * cpr3_sdm660_mmss_calculate_open_loop_voltages() - calculate the open-loop
  *		voltage for each corner of a CPR3 regulator
  * @vreg:		Pointer to the CPR3 regulator
  *
  * Return: 0 on success, errno on failure
  */
-static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages(
+static int cpr4_sdm660_mmss_calculate_open_loop_voltages(
 			struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	const int *ref_volt;
 	int *fuse_volt;
@@ -240,11 +240,11 @@ static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages(
 	if (!fuse_volt)
 		return -ENOMEM;
 
-	ref_volt = msmfalcon_mmss_fuse_ref_volt;
+	ref_volt = sdm660_mmss_fuse_ref_volt;
 	for (i = 0; i < vreg->fuse_corner_count; i++) {
 		fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i],
-			MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i],
-			MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE);
+			SDM660_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i],
+			SDM660_MMSS_VOLTAGE_FUSE_SIZE);
 		cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n",
 			i, fuse_volt[i]);
 	}
@@ -298,7 +298,7 @@ done:
  */
 static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	u32 *ldo_allowed;
 	char *prop_str = "qcom,cpr-corner-allow-ldo-mode";
@@ -341,7 +341,7 @@ done:
  */
 static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	u32 *use_closed_loop;
 	char *prop_str = "qcom,cpr-corner-allow-closed-loop";
@@ -476,7 +476,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread)
 	vreg->ldo_regulator_bypass = BHS_MODE;
 	vreg->ldo_type = CPR3_LDO300;
 
-	rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg);
+	rc = cpr4_sdm660_mmss_read_fuse_data(vreg);
 	if (rc) {
 		cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
 		return rc;
@@ -489,7 +489,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread)
 		return rc;
 	}
 
-	rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg);
+	rc = cpr4_sdm660_mmss_calculate_open_loop_voltages(vreg);
 	if (rc) {
 		cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n",
 			rc);
@@ -548,7 +548,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 		return rc;
 	}
 
-	ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT;
+	ctrl->sensor_count = SDM660_MMSS_CPR_SENSOR_COUNT;
 
 	/*
 	 * MMSS only has one thread (0) so the zeroed array does not need
@@ -559,7 +559,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 	if (!ctrl->sensor_owner)
 		return -ENOMEM;
 
-	ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE;
+	ctrl->cpr_clock_rate = SDM660_MMSS_CPR_CLOCK_RATE;
 	ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4;
 	ctrl->support_ldo300_vreg = true;
 
@@ -572,7 +572,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 			     &ctrl->step_quot_fixed);
 	ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed;
 
-	/* iface_clk is optional for msmfalcon */
+	/* iface_clk is optional for sdm660 */
 	ctrl->iface_clk = NULL;
 	ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk");
 	if (IS_ERR(ctrl->bus_clk)) {
@@ -688,7 +688,7 @@ static int cpr4_mmss_regulator_resume(struct platform_device *pdev)
 /* Data corresponds to the SoC revision */
 static const struct of_device_id cpr4_mmss_regulator_match_table[] = {
 	{
-		.compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator",
+		.compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator",
 		.data = (void *)NULL,
 	},
 };
diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c
index d2f743b8089a..265ca9ed5258 100644
--- a/drivers/regulator/msm_gfx_ldo.c
+++ b/drivers/regulator/msm_gfx_ldo.c
@@ -152,7 +152,7 @@ static struct ldo_config msm8953_ldo_config[] = {
 	{LDO_MAX_OFFSET,	LDO_MAX_OFFSET},
 };
 
-static struct ldo_config msmfalcon_ldo_config[] = {
+static struct ldo_config sdm660_ldo_config[] = {
 	{LDO_ATEST_REG,		0x00000080},
 	{LDO_CFG0_REG,		0x0100A600},
 	{LDO_CFG1_REG,		0x000000A0},
@@ -185,7 +185,7 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = {
 
 enum {
 	MSM8953_SOC_ID,
-	MSMFALCON_SOC_ID,
+	SDM660_SOC_ID,
 };
 
 static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt,
@@ -1516,8 +1516,8 @@ static const struct of_device_id msm_gfx_ldo_match_table[] = {
 		.data = (void *)(uintptr_t)MSM8953_SOC_ID,
 	},
 	{
-		.compatible = "qcom,msmfalcon-gfx-ldo",
-		.data = (void *)(uintptr_t)MSMFALCON_SOC_ID,
+		.compatible = "qcom,sdm660-gfx-ldo",
+		.data = (void *)(uintptr_t)SDM660_SOC_ID,
 	},
 	{}
 };
@@ -1572,8 +1572,8 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev)
 			return rc;
 		}
 		break;
-	case MSMFALCON_SOC_ID:
-		ldo_vreg->ldo_init_config = msmfalcon_ldo_config;
+	case SDM660_SOC_ID:
+		ldo_vreg->ldo_init_config = sdm660_ldo_config;
 		ldo_vreg->ops_type = VOLTAGE;
 		init_data->constraints.valid_ops_mask
 			|= REGULATOR_CHANGE_BYPASS;
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index bd58fcfe3061..ff5eca31323c 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -535,9 +535,9 @@ static struct msm_soc_info cpu_of_id[] = {
 	/* Hamster ID */
 	[306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"},
 
-	/* falcon ID */
-	[317] = {MSM_CPU_FALCON, "MSMFALCON"},
-	[324] = {MSM_CPU_FALCON, "APQFALCON"},
+	/* 660 ID */
+	[317] = {MSM_CPU_660, "SDM660"},
+	[324] = {MSM_CPU_660, "SDA660"},
 
 	/* triton ID */
 	[318] = {MSM_CPU_TRITON, "MSMTRITON"},
@@ -1208,13 +1208,13 @@ static void * __init setup_dummy_socinfo(void)
 		dummy_socinfo.id = 306;
 		strlcpy(dummy_socinfo.build_id, "msmhamster - ",
 			sizeof(dummy_socinfo.build_id));
-	} else if (early_machine_is_msmfalcon()) {
+	} else if (early_machine_is_sdm660()) {
 		dummy_socinfo.id = 317;
-		strlcpy(dummy_socinfo.build_id, "msmfalcon - ",
+		strlcpy(dummy_socinfo.build_id, "sdm660 - ",
 			sizeof(dummy_socinfo.build_id));
-	} else if (early_machine_is_apqfalcon()) {
+	} else if (early_machine_is_sda660()) {
 		dummy_socinfo.id = 324;
-		strlcpy(dummy_socinfo.build_id, "apqfalcon - ",
+		strlcpy(dummy_socinfo.build_id, "sda660 - ",
 			sizeof(dummy_socinfo.build_id));
 	} else if (early_machine_is_msmtriton()) {
 		dummy_socinfo.id = 318;
diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c
index 243b3229f53e..07a1fad03c31 100644
--- a/drivers/thermal/msm-tsens.c
+++ b/drivers/thermal/msm-tsens.c
@@ -937,7 +937,7 @@ static struct of_device_id tsens_match[] = {
 	{	.compatible = "qcom,msmhamster-tsens",
 		.data = (void *)TSENS_CALIB_FUSE_MAP_NONE,
 	},
-	{	.compatible = "qcom,msmfalcon-tsens",
+	{	.compatible = "qcom,sdm660-tsens",
 		.data = (void *)TSENS_CALIB_FUSE_MAP_NONE,
 	},
 	{	.compatible = "qcom,msmtriton-tsens",
@@ -5507,7 +5507,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")))
 		tmdev->tsens_type = TSENS_TYPE3;
 	else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) {
 		tmdev->tsens_type = TSENS_TYPE3;
@@ -5530,7 +5530,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 		(!strcmp(id->compatible, "qcom,msm8937-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msmtitanium-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")) ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens")))))
 			tmdev->tsens_valid_status_check = true;
@@ -5547,7 +5547,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 	if (!strcmp(id->compatible, "qcom,msm8996-tsens") ||
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens")) ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtitanium-tsens"))))) {
 		tmdev->tsens_critical_irq =